July 28, 2026

Hsinchu, Taiwan / Santa Clara, CA – July 27th, 2026 – Andes Technology, a leading supplier of high-performance, energy-efficient RISC-V processor IP and a Founding Premier Member of RISC-V International, and Mirabilis Design today announced a strategic collaboration to deliver system-level architecture models for Andes RISC-V processors. This partnership empowers SoC architects to evaluate and optimize processor-based designs well before RTL development.

As part of this collaboration, Mirabilis Design has developed and validated system-level models for the Andes AX66 multicore and Andes A45 processors using the VisualSim® platform. The models allow architects to explore performance, power, and system behavior early in the design cycle, significantly reducing iteration time and architectural risk.

Why VisualSim?

– Accelerated Design Cycles: Enables architectural exploration months ahead of RTL readiness

– Multi-Domain Modeling: Simulates computation, communication, and software scheduling in a single environment

– Power-Performance Optimization: Delivers early power modeling with task mapping and bandwidth usage

– Trace-Driven Analysis: Helps fine-tune performance using realistic application workloads

About Mirabilis Design Inc.

VisualSim is used by over 75 organizations worldwide in sectors such as semiconductors, automotive, aerospace, and high-performance computing. This latest adoption by a global leader like Samsung further reinforces VisualSim’s position as the go-to platform for system-level innovation.

Mirabilis Design develops VisualSim Architect, the leading platform for modeling, simulating, and analyzing performance and power of complex electronic and embedded systems. Headquartered in Santa Clara, California, Mirabilis serves global clients in semiconductors, automotive, AI, aerospace, and communication infrastructure.